1. Field of the Invention
The present invention relates to a wiring verification system, a wiring verification method, and a wiring verification program product for each supporting design of a printed circuit board, and more particularly to the wiring verification system, the wiring verification method, and the wiring verification computer program product each configured to realize one function or system using a plurality of printed circuit boards.
2. Description of the Related Art
Conventionally, when a printed circuit board (hereinafter, may be simply referred to as a board) is designed, costs have been cut by reducing the number of layers within the board (multi-layered board). However, the reduction in the number of layers within the board causes various malfunctions such as instability in transmission of high-speed signals owing to noise interference between wires passing through each of a plurality of boards. That is, if the number of layers within the board is reduced, it is made difficult to properly distribute wiring constraints so adjusted as to have a wiring condition for stable transmission of high-speed signals through a plurality of wires which is wired for every board. This causes the wiring constraints for a plurality of wires in every board to be complicated. Also, there occurs a necessity to reduce total skew (variation of signals transmitted through a plurality of wires) in a plurality of wires passing through a plurality of boards.
To solve such malfunction problems as mentioned above, the conventional technique of board designing employs two kinds of skew reducing methods, one being a division-type verification method in which a plurality of boards is divided for wire verification and another being a collective-type verification method in which a plurality of boards is verified collectively. The division-type verification method is a method in which wiring constraints is totally observed by dividing wiring constraints for every board and by complying with the wiring constraints in units of boards, which enables simplification of wiring constraints on the entirety of the boards. The collective-type verification method is a method in which all data is referenced to in a state where a plurality of boards is connected and has a merit in which no division of an allowable error in each board and of wiring constraints is required.
Moreover, a technology is disclosed in, for example, Japanese Patent Application Laid-open No. 2006-252285 to support designing of printed circuit boards, which is capable of performing designing work on a plurality of layers of boards that makes up one function or system. According to this technology, by synthesizing various pieces of circuit connection information about a plurality of boards into one piece of information or, if necessary, by dividing various pieces of circuit connection information into a plurality of pieces of wiring information for each board, wiring constraints information and/or designing constraint information can be collectively managed. This enables effective designing work of combined boards obtained by synthesizing functions or systems and further shortening of designing period, cost reduction, improvement of designing quality.
However, the above division-type verification method has a demerit in that the wiring constraints on an allowable error of the board in its entirety are stringent since the allowable error of the wiring constraints is equally divided for every board and, therefore, even if the allowable error of wiring constraints is satisfied in one board, the allowable error of wiring constraints is not satisfied in another board. Moreover, there is a fear that, since the wiring constraints cannot be divided on an equal condition for every board, the wiring constraints vary depending upon high-speed signals flowing through each wire, which makes the wiring constraints complicated and causes degradation of quality of boards.
In the collective-type verification method, the division of the allowable error and the division of wiring constraints are not required, however, all data in the state where a plurality boards is connected thereto is referenced and, therefore, the scale of data to be referenced thereto at one time is increased. As a result, the time for performing wiring verification is lengthened, which produces a fear of degradation of real time properties of the wiring constraints. Further, at the time of describing conditions for the wiring constraints, identifying designations of starting and ending points of external wires other than wires for the board to be designed is required, which causes complicated handling of conducting wiring verification. It is also necessary that paths other than the path of the board to be an object of wiring verification have been already wired and, as a result, reversion of work for re-verification at the time of error detection by wiring verification is increased, which is another demerit.